Sterownik PFC o podwójnej fazie i przełączaniu międzyfazowym UCC28060 — przewodnik inżynieryjny
1. Overview and Applications
The UCC28060 from Texas Instruments is a high-performance, dual-phase interleaved power factor correction (PFC) controller IC designed for:
- Server power supplies
- Industrial power systems
- High-power LED drivers (>200W)
- AC-DC converters requiring compliance with IEC61000-3-2 standards
Key design advantages include:
- THD reduction below 5% at full load
- Power factor >0.99
- Reduced input current ripple through phase interleaving
2. Core Features Analysis
2.1 Dual-Channel Interleaved Operation
Two 180° phase-shifted boost converters effectively double the ripple frequency, allowing:
- Input capacitor size reduction by 30-50%
- Lower RMS current in output capacitors
2.2 Critical Functionalities
- Frequency dithering: ±5% frequency modulation for reduced EMI peaks
- Programmable frequency: 20kHz to 250kHz (set via external resistor)
- Soft-start: Adjustable 10-100ms ramp-up via capacitor
- Protection features:
- Brown-out protection (UVLO)
- Output overvoltage (OVP) with 2.5% accuracy
- Thermal shutdown at 150°C
3. Application Circuit Design
Note: Always refer to TI reference design PMP4302 for baseline component values.
3.1 Critical Components Selection
| Component | Selection Criteria | Recommended Parts |
|---|---|---|
| Boost Inductor | Low core loss at switching frequency, 20% current margin | Würth Elektronik 7443630220 or Coilcraft SER2918H |
| MOSFET | RDS(on) <80mΩ, VDSS ≥600V | Infineon IPP60R180P6 or STF20NM60FD |
| Current Sense Resistor | 1% tolerance, TCR <100ppm> | Vishay WSLP2726 or Bourns CSS2H-5930 |
3.2 Common Debugging Issues
- Channel imbalance: Check gate drive symmetry and current sense routing
- PF degradation:
- Startup failures: Verify soft-start capacitor value (typically 100nF)
4. Competitive Analysis
| Kontroler | Channels | Interleaving | Frequency Dithering | Best For |
|---|---|---|---|---|
| UCC28060 | 2 | Tak | Tak | 200-1000W balanced designs |
| UCC28070 | 2 | Tak | NIE | Cost-sensitive interleaved PFC |
| L6562D | 1 | NIE | NIE | <100W basic PFC |
5. PCB Layout Guidelines
- Current sense paths: Keep traces <10mm long with Kelvin connection
- Gate drives: Maintain equal trace lengths (±5mm) between channels
- Grounding: Star-point connection for analog and power grounds
- EMI reduction: Minimize loop areas in:
- Switch node (Q1/Q2 drains)
- Input capacitor connections
6. Performance Data
- Typical efficiency: 96.2% @ 230VAC, 500W load
- THD: 3.8% at full load (meets EN61000-3-2 Class D)
- Startup current: <50μA during VCC charging
7. Design Recommendations
Recommended when:
- Input power exceeds 200W
- System requires <5% THD
- Design targets 80Plus Titanium certification
Not recommended for:
- Low-cost designs under 100W
- Non-PFC applications
8. Support Resources
For complete design packages including:
- SPICE simulation models
- Gerber files for reference designs
- BOM optimization services
Contact TI authorized distributors or visit TI's official product page.
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